The present invention relates to a MIS semiconductor device that has a fine structure for realizing high integration of a semiconductor integrated circuit and is capable of operating at high speed and low consumption power and a method for fabricating the same.
In accordance with increase in integration of semiconductor integrated circuits, there is a demand for refinement of MIS semiconductor devices, in particular, MIS transistors, and for this purpose, a MIS transistor with shallow junction is desired.
A method for fabricating a conventional MIS transistor will now be described with reference to FIGS. 8A through 8E.
First, as shown in FIG. 8A, indium (In) ions, that is, a P-type dopant, are implanted at acceleration energy of 200 keV and a dose of approximately 1xc3x971012/cm2 into a semiconductor substrate 101 of P-type silicon having a principal plane with a  less than 100 greater than -oriented zone axis. After the implantation, annealing is carried out, so as to form a P-type channel diffusion layer 110a serving as a channel region in an upper portion of the semiconductor substrate 101. Subsequently, a gate insulating film 102 with a thickness of approximately 2.2 nm is formed on the semiconductor substrate 101 and a gate electrode 103 of polysilicon with a thickness of approximately 200 nm is formed thereon.
Next, as shown in FIG. 8B, with the gate electrode 103 used as a mask, In ions, that is, a P-type dopant, are implanted into the semiconductor substrate 101 at acceleration energy of 100 keV and a dose of approximately 1xc3x971014/cm2. At this point, a current density for implanting the In ions is approximately 1000 xcexcA/cm2, and the ions are implanted at an angle of approximately 0 through 7 degrees against the normal line of the substrate. Subsequently, arsenic (As) ions, that is, an N-type dopant, are implanted into the semiconductor substrate 101 at acceleration energy of 10 keV and a dose of 5xc3x971014/cm2. Thereafter, annealing is carried out at a high temperature for a short period of time, so as to form a P-type dopant diffusion layer 104A and an N-type heavily-doped diffusion layer 105A with shallow junction in a source/drain region of the semiconductor substrate 101.
Then, as shown in FIG. 8C, a silicon nitride film with a thickness of approximately 50 nm is deposited on the entire surface of the semiconductor substrate 101 at approximately 700xc2x0 C., and the deposited silicon nitride film is subjected to anisotropic etching, thereby forming a sidewall 106 on the side face of the gate electrode 103. The sidewall 106 may be formed from a silicon oxide film instead of the silicon nitride film.
Next, as shown in FIG. 8D, with the gate electrode 103 and the sidewall 106 used as a mask, As ions, that is, an N-type dopant, are implanted into the semiconductor substrate 101 at acceleration energy of 30 keV and a dose of approximately 3xc3x971015/cm2, and then annealing is carried out at a high temperature for a short period of time. Thus, an N-type source/drain heavily-doped diffusion layer 107 with deep junction is formed in the source/drain region of the semiconductor substrate 101, an N-type extension region heavily-doped diffusion layer 105B with shallower junction than the source/drain heavily-doped diffusion layer 107 is formed on the inside of the source/drain heavily-doped diffusion layer 107, and a P-type pocket region of heavily-doped diffusion layer 104B is formed under the extension region heavily-doped diffusion layer 105B.
Next, as shown in FIG. 8E, after a metal film of cobalt or titanium with a thickness of approximately 10 nm and a titanium nitride film with a thickness of approximately 20 nm are successively deposited on the semiconductor substrate 101 by sputtering, annealing is carried out at approximately 550xc2x0 C. for 10 seconds. Thereafter, the titanium nitride film and an unreacted portion of the metal film are removed by selectively etching them with a mixture of sulfuric acid, hydrogen peroxide and water. Subsequently, annealing is carried out at approximately 800xc2x0 C. for ten seconds, so as to form a cobalt silicide layer 108 with a thickness of approximately 30 nm in a self-alignment manner in upper portions of the gate electrode 103 and the source/drain heavily-doped diffusion layer 107.
In this manner, in the conventional method for fabricating a MIS transistor, In ions, that is, heavy ions, are used for the ion implantation for forming the pocket heavily-doped diffusion layer 104B, so as to realize abrupt dopant profile with shallow junction.
In the conventional method for fabricating a MIS transistor, however, since the heavy ions are used for forming the pocket heavily-doped diffusion layer 104B, an amorphous layer is formed in the semiconductor substrate 101 when the ions are implanted at a dose exceeding a predetermined dose because the implantation of the heavy ions largely damages the crystal of the semiconductor substrate 101. Furthermore, through the annealing carried out after the implantation, an EOR (end-of-range) dislocation loop defect layer is formed below the amorphous-crystal interface, and the heavy ions such as In ions are largely segregated in the EOR dislocation loop defect layer.
In particular, in the dopant implantation using heavy ions, the amorphous-crystal interface is formed in a position deeper than the concentration peek of the dopant, and hence, the junction plane obtained after diffusion of the extension heavily-doped diffusion layer 105B is formed in a position deeper than a designed depth. Furthermore, when the EOR dislocation loop defect layer is formed in the vicinity of the junction plane of the extension region of heavily-doped diffusion layer 105B, junction leakage is disadvantageously caused.
However, unless heavy ions with a relatively large mass number is used for forming a heavily-doped diffusion layers such as a pocket region and an extension region, it is very difficult to attain shallower junction with currently existing transient enhanced diffusion suppressed. For example, in a CMOS transistor with a design rule of 0.1 xcexcm, junction depth of approximately 20 nm through 30 nm is required of the extension heavily-doped diffusion layer 105B. In this case, the As ions are probably moved by as large as approximately several tens nm owing to the transient enhanced diffusion caused by the annealing carried out at a low temperature for forming the sidewall 106. Accordingly, when a MIS transistor is further refined, even when the ion implantation is carried out at small acceleration energy, the junction depth of the extension heavily-doped diffusion layer 105B is unavoidably increased to exceed a target value through the subsequent annealing.
The transient enhanced diffusion is a phenomenon that excess point defects and an implanted dopant are diffused through the interaction, resulting in diffusing the dopant more largely than the diffusion coefficient in the thermal equilibrium state.
The present invention was devised for overcoming the aforementioned conventional problems, and an object is suppressing occurrence of dislocation loop defects derived from heavy ions while using the heavy ions indispensable for attaining shallow junction in forming heavily-doped diffusion layers serving as an extension region and a pocket region.
In order to achieve the object, in a MIS semiconductor device and a fabrication method for the same according to the invention, a semiconductor substrate capable of suppressing the formation of a defect layer is used, or heavy ions are implanted so as to reduce implantation damage caused during the implantation and so as to minimally form a defect layer in a semiconductor substrate itself.
Specifically, the first semiconductor device of this invention comprises a heavily-doped diffusion layer formed, by using a dopant ion having a relatively large mass number, in an epitaxial region of silicon included in at least an upper portion of an epitaxial semiconductor substrate.
In general, a semiconductor obtained by the epitaxial growth is superior in the crystal quality to a semiconductor obtained by the general rotational pulling (CZ) method. Accordingly, since the semiconductor device of this invention includes the heavily-doped diffusion layer formed by implantation and diffusion of the dopant heavy ions in the epitaxial region, EOR dislocation loop defects are less caused than in a general semiconductor substrate. As a result, the heavy ions are minimally segregated in a region below an amorphous-crystal interface, and hence, the semiconductor device can be refined with a leakage current derived from the segregation suppressed.
In the first semiconductor device, the epitaxial region preferably has a  less than 110 greater than -oriented zone axis.
In the first semiconductor device, the heavily-doped diffusion layer is preferably formed by using, as the dopant ion, an indium ion at a dose of 5xc3x971013/cmxe2x88x922 or more. Since the heavily-doped diffusion layer can be thus changed into an amorphous layer, channeling of another dopant ion subsequently implanted can be suppressed, resulting in definitely forming the heavily-doped diffusion layer so as to have shallow junction.
In the first semiconductor device, the heavily-doped diffusion layer preferably corresponds to a pocket region of heavily-doped diffusion layer of a MIS semiconductor device, and the MIS semiconductor device preferably includes a gate electrode formed above the epitaxial region with a gate insulating film sandwiched therebetween; a source/drain heavily-doped diffusion layer of a first conductivity type formed in a source/drain region of the epitaxial region at a distance from a region below a side face of the gate electrode; an extension region heavily-doped diffusion layer of the first conductivity type formed in the epitaxial region between the source/drain heavily-doped diffusion layer and the region below the side face of the gate electrode and having shallower junction than the source/drain heavily-doped diffusion layer; and the pocket region of heavily-doped diffusion layer of a second conductivity type formed in the epitaxial region under the extension heavily-doped diffusion layer. In this manner, the pocket region of heavily-doped diffusion layer is formed from the heavily-doped diffusion layer of this invention, and hence, the extension region heavily-doped diffusion layer and the pocket region of heavily-doped diffusion layer formed between the source/drain heavily-doped diffusion layers can attain shallow junction.
In this case, the extension region heavily-doped diffusion layer is preferably formed by using an antimony ion as a dopant. In this manner, since an antimony ion is an N-type heavy ion, the junction depth of the extension region heavily-doped diffusion layer can also definitely attain shallow junction.
The second semiconductor device of this invention comprises a heavily-doped diffusion layer formed, by using a dopant ion having a relatively large mass number, in a semiconductor substrate having a  less than 110 greater than -oriented zone axis.
Since the second semiconductor device uses the semiconductor substrate having the  less than 110 greater than -oriented zone axis, the implanted heavy ion is channeled and hence less collides with a silicon atom, resulting in reducing implantation damage of the semiconductor substrate. As a result, formation of interstitial silicon is suppressed and EOR dislocation loop defects are less caused, so that the heavy ions can be minimally segregated in the region below the original amorphous-crystal interface.
In the second semiconductor device, the heavily-doped diffusion layer is preferably formed by using, as the dopant ion, an indium ion at a dose of 5xc3x971013/cmxe2x88x922 or more.
In the second semiconductor device, the heavily-doped diffusion layer preferably corresponds to a pocket heavily-doped diffusion layer of a MIS semiconductor device, and the MIS semiconductor device preferably includes a gate electrode formed above the semiconductor substrate with a gate insulating film sandwiched therebetween; a source/drain heavily-doped diffusion layer of a first conductivity type formed in a source/drain region of the semiconductor substrate at a distance from a region below a side face of the gate electrode; an extension region heavily-doped diffusion layer of the first conductivity type formed in the semiconductor substrate between the source/drain heavily-doped diffusion layer and the region below the side face of the gate electrode and having shallower junction than the source/drain heavily-doped diffusion layer; and the pocket region of heavily-doped diffusion layer of a second conductivity type formed in the semiconductor substrate under the extension heavily-doped diffusion layer.
In this case, the extension region heavily-doped diffusion layer is preferably formed by using an antimony ion as a dopant.
The first method for fabricating a semiconductor device of this invention comprises a step of forming a heavily-doped diffusion layer by implanting a dopant ion having a relatively large mass number into an epitaxial region of silicon included in at least an upper portion of an epitaxial semiconductor substrate.
Since a pocket region of heavily-doped diffusion layer is formed by implantation and diffusion of the dopant heavy ion in the epitaxial region of silicon in the first method for fabricating a semiconductor device, the heavy ion is minimally segregated in the region below the original amorphous-crystal interface. Accordingly, the semiconductor device can be refined with a leakage current derived from the segregation suppressed.
In the first method for fabricating a semiconductor device, the epitaxial region preferably has a  less than 110 greater than -oriented zone axis.
In the first method for fabricating a semiconductor device, the heavily-doped diffusion layer is preferably formed by using, as the dopant ion, an indium ion at a dose of 5xc3x97103/cm2 or more. Since the first dopant layer can be thus changed into an amorphous layer, the channeling of the second dopant subsequently implanted can be suppressed. Accordingly, the extension region heavily-doped diffusion layer and the pocket region of heavily-doped diffusion layer can definitely attain shallow junction, resulting in realizing a semiconductor device with high driving power.
In the first method for fabricating a semiconductor device, the heavily-doped diffusion layer preferably corresponds to a pocket region of heavily-doped diffusion layer of a MIS semiconductor device, and the method for fabricating the MIS semiconductor device preferably includes the steps of forming a gate electrode above the epitaxial region with a gate insulating film sandwiched therebetween; forming a first dopant layer to be used as the pocket region of heavily-doped diffusion layer by implanting a first dopant of a first conductivity type corresponding to the dopant ion into the epitaxial region with the gate electrode used as a mask; forming a second dopant layer to be used as an extension region heavily-doped diffusion layer by implanting a second dopant of a second conductivity type into the epitaxial region to have shallower junction than the first dopant layer with the gate electrode used as a mask; and forming a sidewall on a side face of the gate electrode, and forming a third dopant layer to be used as a source/drain heavily-doped diffusion layer by implanting a third dopant of the second conductivity type into the epitaxial region to have deeper junction than the second dopant layer with the gate electrode and the sidewall used as a mask. In this manner, the extension region heavily-doped diffusion layer formed between the source/drain heavily-doped diffusion layers and the pocket region of heavily-doped diffusion layer formed under the extension region heavily-doped diffusion layer can attain shallow junction.
In this case, the first method for fabricating a semiconductor device preferably further comprises a step of forming a fourth dopant layer to be used as a channel diffusion layer by implanting a fourth dopant of the first conductivity type into the epitaxial region before forming the gate electrode. In this manner, when an In ion, that is, a heavy ion, is used as a dopant for the channel diffusion layer, a dopant concentration distribution in which the concentration of the In ions is low in the vicinity of the surface of the epitaxial region and is abrupt in a position slightly deeper than the vicinity of the surface can be attained. Accordingly, the semiconductor device can be refined without degrading the driving power of the transistor.
In this case, the second dopant is preferably an antimony ion.
The second method for fabricating a semiconductor device of this invention comprises a step of forming a heavily-doped diffusion layer by implanting a dopant ion having a relatively large mass number into a semiconductor substrate under conditions for suppressing dislocation loop defects caused in the semiconductor substrate.
In the second method for fabricating a semiconductor device, the occurrence of dislocation loop defects can be suppressed in the semiconductor substrate during the implantation of the dopant ion for forming the heavily-doped diffusion layer. Therefore, the heavy ion is minimally segregated in the region below the amorphous-crystal interface, and hence, a leakage current derived from the segregation can be suppressed.
In the second method for fabricating a semiconductor device, the heavily-doped diffusion layer is preferably formed by using, as the dopant ion, an indium ion at a dose of 5xc3x971013/cmxe2x88x922 or more.
In the second method for fabricating a semiconductor device, the dopant ion is preferably implanted at a current density of approximately 100 xcexcA/cm2 or less.
In the second method for fabricating a semiconductor device, the dopant ion is preferably implanted at an angle of approximately 30 degrees or more against a vertical direction to a substrate surface of the semiconductor substrate.
In the second method for fabricating a semiconductor device, the heavily-doped diffusion layer preferably corresponds to a pocket heavily-doped diffusion layer of a MIS semiconductor device, and the method for fabricating the MIS semiconductor device preferably includes the steps of forming a gate electrode above the semiconductor substrate with a gate insulating film sandwiched therebetween; forming a first dopant layer to be used as the pocket region of heavily-doped diffusion layer by implanting a first dopant of a first conductivity type corresponding to the dopant ion into the semiconductor substrate with the gate electrode used as a mask; forming a second dopant layer to be used as an extension region heavily-doped diffusion layer by implanting a second dopant of a second conductivity type into the semiconductor substrate to have shallower junction than the first dopant layer with the gate electrode used as a mask; and forming a sidewall on a side face of the gate electrode, and forming a third dopant layer to be used as a source/drain heavily-doped diffusion layer by implanting a third dopant of the second conductivity type into the semiconductor substrate to have deeper junction than the second dopant layer with the gate electrode and the sidewall used as a mask.
In this case, the second method for fabricating a semiconductor device preferably further comprises a step of forming a fourth dopant layer to be used as a channel diffusion layer by implanting a fourth dopant of the first conductivity type into the semiconductor substrate before forming the gate electrode.
In this case, the second dopant is preferably an antimony ion.
The third method for fabricating a semiconductor device of this invention comprises a step of forming a heavily-doped diffusion layer by implanting a dopant ion having a relatively large mass number into a semiconductor substrate having a  less than 110 greater than -oriented zone axis.
In the third method for fabricating a semiconductor device, in implanting the dopant ion into the semiconductor substrate for forming the heavily-doped diffusion layer, the heavy ion is channeled in the semiconductor substrate having the  less than 110 greater than -oriented zone axis. Therefore, the implantation damage of the semiconductor substrate is reduced and the formation of interstitial silicon is suppressed, and hence, EOR dislocation loop defects are less caused, resulting in suppressing a leakage current derived from the segregation. Also, even when the heavy ion is channeled, the implantation range is less largely increased owing to the mass effect of the heavy ion than that of a light ion, and hence, shallow junction can be realized.
In the third method for fabricating a semiconductor device, the heavily-doped diffusion layer preferably corresponds to a pocket region of heavily-doped diffusion layer of a MIS semiconductor device, and the method for fabricating the MIS semiconductor device preferably includes the steps of forming a gate electrode above the semiconductor substrate with a gate insulating film sandwiched therebetween; forming a first dopant layer to be used as the pocket region of heavily-doped diffusion layer by implanting a first dopant of a first conductivity type corresponding to the dopant ion into the semiconductor substrate with the gate electrode used as a mask; forming a second dopant layer to be used as an extension region heavily-doped diffusion layer by implanting a second dopant of a second conductivity type into the semiconductor substrate to have shallower junction than the first dopant layer with the gate electrode used as a mask; and forming a sidewall on a side face of the gate electrode, and forming a third dopant layer to be used as a source/drain heavily-doped diffusion layer by implanting a third dopant of the second conductivity type into the semiconductor substrate to have deeper junction than the second dopant layer with the gate electrode and the sidewall used as a mask.
The third method for fabricating a semiconductor device preferably further comprises a step of forming a fourth dopant layer to be used as a channel diffusion layer by implanting a fourth dopant of the first conductivity type into the semiconductor substrate before forming the gate electrode.
In the third method for fabricating a semiconductor device, the second dopant is preferably an antimony ion.